1. Technical Field
The present disclosure relates to semiconductor circuits, and more particularly, to a semiconductor integrated circuit including a power gate or a multi-threshold CMOS device (MTCMOS) and a method of fabricating the same, in order to reduce a leakage current in a stop mode.
2. Discussion of Related Art
At present, performance of VLSI (Very Large Scale Integration) circuits and a combination capability of realizing respective circuits in one chip have been undergoing remarkable development. In particular, the increased number of image systems and radio communication equipment and the like requires circuits capable of performing various complicated functions. In order to perform such various complicated functions in the circuit, relatively more transistors should be combined. But excessive power consumption in the circuit limits the number of transistors that can be combined. The excessive power consumption increases a generation of heat in the circuit, and the heat degrades the performance of the circuit, as well as the system employing the circuit.
Further, excessive power consumption may shorten a change period of secondary batteries in portable instruments that use the secondary batteries as the main power supply source. Thus, lessening a power consumption is a necessarily required object in designing semiconductor integrated circuits.
In general, the main causes of power consumption in a MOS circuit may be based on a switching power and a short-circuit current, as well as being based on a leakage current and the like. More specifically, the power consumption based on the leakage current occurs by a leakage current generated in a stop mode. The stop mode herein may also indicate a standby state in which the MOS circuit does not operate.
FIG. 1 is a current diagram illustrating a conventional art circuit to reduce a leakage current generated in a stop mode.
FIG. 1 illustrates a structure of power gate including a MOS logic 10 and a switching transistor PM1.
The MOS logic 10 is connected with a power terminal and a ground terminal, and operates by receiving a power source voltage VDD when the switching transistor PM1 is turned on. The MOS logic 10 has a relatively low threshold voltage as compared with the switching transistor PM1. The MOS logic 10 may be a circuit constructed of, for example, a number of MOS transistors, such as a CMOS inverter.
The switching transistor PM1 is a PMOS transistor. Thus, when a switching signal S1 has a low level, the switching transistor PM1 is turned on, and when the switching signal S1 has a high level, the switching transistor PM1 is turned off.
The switching transistor PM1 may be realized by a level under M1 or M2 from among a plurality of metal layers of, for example, M0, M1, M2, M3 . . . from a lower part of an upper part of a vertical structure of the transistor. That is, the switching transistor PM1 may be designed so as not to influence the metal layers next to layers M1 or M2.
The number of switching transistors PM1 required for a semiconductor integrated circuit of FIG. 1 may be determined by the highest power of the MOS logic 10. For example, in assuming a driving current of one switching transistor PM1 is 1 μÅ, a leakage current is 1nÅ, and an anticipated greatest power of the MOS logic is 100 mW@1.0V/400 Mhz; the required number of switching transistors is 100,000.
Further, leakage current in the stop mode is 1nÅ*100,000, that is, 100 μÅ. In such systematic design, when the highest power required for the semiconductor integrated circuit is 200 mW, the required number of switching transistors is 200,000, in other words, 100,000 more than the number when 100 mW is the highest power. In order to meet such requirement it is difficult to find an appropriate method except a revision of the circuit design.
If the revision is not performed, the semiconductor integrated circuit may face a performance drop or leakage current increase.
That is, in case a pre-computed or simulated leakage current value actually has an error in a semiconductor integrated circuit on a wafer, the revision should be performed, or a product development or production impossibility due to a performance drop or leakage current increase should be accepted without any other solution, further bringing about a yield decrease or performance drop.
Even though the revision is performed, a mask revision is needed from a transistor level, so that the product development may be delayed.
FIG. 2 is a circuit diagram illustrating another example of a conventional art circuit to reduce a leakage current generated in a stop mode.
FIG. 2 illustrates a structure of MTCMOS (Multi Threshold CMOS (Complementary Metal Oxide Semiconductor)) having a MOS logic 20 and a switching transistor NM1.
The MTCMOS is a semiconductor integrated circuit having a structure to control a threshold voltage of the MOS logic 20, and the switching transistor NM1 is an NMOS transistor.
In an operating mode, the switching transistor NM1 is turned on by a switching signal S2 of high level, and in a stop mode the switching transistor NM1 is turned off by the switching signal S2 at a low level.
Similar problems may occur in the MTCMOS structure of FIG. 2 just as in in the power gate structure shown in FIG. 1, such as a dependency upon a circuit revision, or a product development or production impossibility based on a performance drop or leakage current increase, or a yield decrease or performance drop.
FIG. 3 is a circuit diagram illustrating another example of a conventional art circuit to reduce leakage current generated in a stop mod.
A MOS logic 30 may include transistors having a low threshold voltage. A switching transistor PM3 having a high threshold voltage may be positioned between the power source voltage VDD and the MOS logic 30, and a switching transistor NM3 having a high threshold voltage is positioned between the MOS logic 30 and a ground voltage VSS.
The switching transistor PM3 may be a PMOS transistor and the switching transistor NM3 may be an NMOS transistor.
When the MOS logic 30 operates, the switching transistors PM3, NM3 having a high threshold voltage are turned on, supplying power to the MOS logic 30. While the MOS logic 30 is in the stop mode, the switching transistor PM3 controlled by a switching signal S3 is turned off through a high threshold voltage of the switching transistor PM3, and the switching transistor NM3 controlled by a switching signal S5 is also turned off, thus reducing a leakage current of the circuit.
The MOS logic 30 connected between a virtual power node N3 and a virtual ground node N4 has a low threshold voltage.
In the operating mode of the circuit shown in FIG. 3, the switching signal S3 has a low level, and the switching signal S4 has a high level. Then, the switching transistor PM3 and the switching transistor NM3 are turned on, and the virtual power node N3 and the virtual ground node N4 operate by an actual power source voltage and a ground voltage, thereby reducing a resistance of the circuit.
When in the stop or standby mode, the switching signal S3 has a high level and the switching signal S4 has a low level, the switching transistor PM3 and the switching transistor NM3 having a high threshold voltage are both turned off. Thus, a leakage current may be reduced in the stop mode.
This approach, however, also has problems similar to those in the power gate structure and the MTCMOS structure shown in FIGS. 1 and 2. For example, such problems involve a dependency upon the circuit revision, or a product development or production impossibility based on a performance drop or leakage current increase, or a shield decrease. Also, a mask revision is required from a transistor level, thereby delaying a development schedule.
In the case of a semiconductor integrated circuit including a power gate or MTCMOS significantly influencing a performance or leakage current, a size, number and structure of an NMOS transistor or PMOS transistor involve some estimation error; and a solution therefore is necessarily required through a semiconductor integrated circuit including a power gate or MTCMOS structure to more easily perform a revision of the semiconductor integrated circuit and satisfactorily provide an operating environment of the circuit with consideration of a leakage current and performance of the stop mode.